Integrated circuit with stop layer and associated fabrication process
Integrated circuit with stop layer and associated fabrication process
Gayet, P and Granger, E
US Patent 6,762,497 2004
Abstract : A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form łdots